China's Seichi Tech has won larger orders for its memory test equipment — that much is confirmed. What remains unproven, as XenoSpectrum reports, is whether any of those orders cover high-bandwidth memory (HBM), the DRAM category now dominating AI-accelerator roadmaps.

The distinction matters commercially and technically. Conventional DDR and LPDDR testers validate devices whose interfaces run at a few gigatransfers per second per pin over standard package interconnects. HBM stacks dram dies through silicon interposers and microbumps, presenting the tester with thousands of parallel contacts, multi-gigabit signals across dense through-silicon via structures, and thermal conditions set by stacked-die self-heating. A tester platform qualified for DDR5 does not automatically qualify for HBM3E; the probe card, the timing channels, and the contact resistance budget all change. So an order-book increase that mixes HBM into the shipment mix would signal genuine design-win maturity. An increase built on legacy DDR5 and LPDDR5X volume signals scale, not capability.

What does the order growth actually establish?

It establishes demand. China's memory producers — CXMT foremost among them — are expanding DDR5 and LPDDR capacity and, like every other dram maker, are pushing toward HBM qualification for AI customers. That expansion drives tester procurement regardless of node. Seichi Tech, as one of the few domestic ATE suppliers in the memory segment, sits directly in that procurement path as fabs work to qualify non-US equipment chains.

What the orders do not yet establish, on the available reporting, is HBM-specific adoption. XenoSpectrum's framing is explicit on this point: bigger orders, yes; proven HBM deployment, no. No customer, no volume figure, and no HBM generation has been publicly tied to Seichi's platform.

Why HBM test is the credibility bar

HBM is the hardest test problem in the memory business today. The stacked architecture makes repair and known-good-die screening economically mandatory: a faulty die discovered after stack assembly scrapes the entire tower, not one chip. Tester throughput, pattern depth for structural fault coverage, and the ability to exercise stacked dies through limited access paths all become procurement criteria that DDR testers were never stressed against.

For a domestic Chinese supplier, HBM qualification would carry a second signal — that the full toolchain around the tester, from probe interfaces to calibration and service support, meets the uptime and correlation requirements of a fab running AI-grade memory at yield. Until a named HBM order or fab confirmation appears, that signal is absent.

The adoption question

The order growth shows China's fabs will buy domestic memory ATE at increasing scale. The open question for buyers and competitors alike: when the first high-volume HBM line needs its tester fleet, will Seichi Tech's platform be on the qualified list — and will the company disclose the customer and generation that proves it?